/* ns_geode.h */ /* * Copyright (c) 2001 Bruce R. Montague * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF * SUCH DAMAGE. */ /* *-------------------------------------------------------------- * National Semiconductor Geode Native Audio device definitions. * 1-August-2002 * *-------- * This file contains #defines that describe the hardware registers * of the National Semiconductor Geode native PCI "audio function". * The Geode is a family of x86 compatible CPUs and support chips. * At one time the audio device was integrated into the Cx5530 Geode I/O * Companion (that is, "southbridge"), however, currently the CPU and * PCI audio function core might be found integrated on a single chip. * * This file contains only hardware defines from the National * datasheet. All #define's configuring the driver itself are found * in the companion file, "ns_geode.c". * *-------- * The Geode "Audio Engine" has 6 PCI Bus Masters that can be * considered independent DMA engines. Each is controlled by 3 * registers. Each of these bus masters has a hard-wired function * (they insert data into fixed AC'97 serial codec protocol "slots"): * * DMA 0 - 32-bit stereo output (PLAY device, 2 16-bit PCM channels). * DMA 1 - 32-bit stereo input (RECORD device, 2 16-bit PCM channels). * DMA 2 - 16-bit mono output (MONO-PLAY). * DMA 3 - 16-bit mono input (MONO-RECORD). * DMA 4 - 16-bit mono output, codec slot programmable. * DMA 5 - 16-bit mono input, codec slot programmable. * * The DMA engines are refered to in the code using: * * DMA 0 - DMA_PLAY_* * DMA 1 - DMA_RECORD_* * DMA 2 - DMA_PLAY_MONO_* * DMA 3 - DMA_RECORD_MONO_* * * This driver assumes the codec is a National LM4549 AC'97 codec. * (other AC'97 codec might work, however there is a specific check * for the LM4549 VENDOR ID that would have to be disabled). * *-------- * The PCI Audio Function is accessed via the normal PCI configuration * mechanism (I/O space 0xCF8 (address) and 0xCFC (data)). PCI * Function 3 registers constitute the XpressAUDIO configuration * registers, which are largely similar to those of any PCI function * header. One of these, register 0x10, is the F3BAR register, the * "Base Address" register. This contains the physical memory * address of Audio control memory "in" the PCI audio device, that * is, memory-mapped audio-specific registers. The command and * status register of the codec and the registers that control each * of the 6 bus engines are in these memory-mapped registers. * * Each PCM "channel" corresponds to a PCI bus master. The bus masters * ("DMA engines") are controlled by arrays of "Physical Region * Descriptors" (PRDs). Each element of a PRD array contains a * physical memory pointer and a buffer length and flags word. The * bus master is programmed with the physcial memory address of the * PRD array via one of the memory-mapped bus-engine control registers. * The bus master can process successive PRD entries automatically. * Typically, a flag in each PRD entry will cause a bus master * interrupt at the completion of the "DMA" corresponding to the * PRD entry. The flags of the last PRD entry usually are used not * to control a DMA operation, but instead to loop the bus master * back to process the first element of the PRD array (thus supporting * overlapped buffering). *-------------------------------------------------------------- */ #define PCI_CONFIG_ADR 0x0CF8 #define PCI_CONFIG_DATA 0x0CFC #define GEODE_PCI_HDR_BAR 0x10 /* Geode memory-mapped PCI audio regs (via F3BAR) */ #define CODEC_STATUS_REG 0x08 #define CODEC_CMD_REG 0x0C /*--- Audio Bus Master 0: 32-bit Output to codec, left/right 16-bit PCM channels. */ #define DMA_PLAY_CMD 0x20 #define DMA_PLAY_STATUS 0x21 #define DMA_PLAY_PRD_ADR 0x24 /*--- Audio Bus Master 1: 32-bit Input from codec, left/right 16-bit PCM channels. */ #define DMA_RECORD_CMD 0x28 #define DMA_RECORD_STATUS 0x29 #define DMA_RECORD_PRD_ADR 0x2C /*--- Audio Bus Master 2: 16-bit PCM output to codec, mono. */ #define DMA_PLAY_MONO_CMD 0x30 #define DMA_PLAY_MONO_STATUS 0x31 #define DMA_PLAY_MONO_PRD_ADR 0x34 /*--- Audio Bus Master 3: 16-bit PCM input from codec, mono. */ #define DMA_RECORD_MONO_CMD 0x38 #define DMA_RECORD_MONO_STATUS 0x39 #define DMA_RECORD_MONO_PRD_ADR 0x3C /* *-------------------------------------------------------------- * The "DMA engines" are connected to an AC'97 codec. The codec * can be considered A/D and D/A converters for all the channels, * with per-channel volume controls. The AC'97 spec defines a * number of registers in the codec (mostly volume controls, but * also sample format and speed). * * The codec has a synchronous serial interface to the PCI audio * controller managed via the PCI Audio Function memory-mapped * registers. * * All reads and writes of the 8-bit registers internal to the codec * (that is, the AC'97 registers) are performed by writing 32-bit * command words to the PCI-memory-mapped CODEC_CMD_REG. The top * 8-bits of the command word indicate which register is to be read * or written, and the top bit indicates if the operation is a read * or write (1 is read). On a write, the bottom 16-bits of the * CODEC_CMD_REG command word will be written over the serial link * to the codec target register. A read from the codec puts the * designated codec register into the low 16-bits of CODEC_STATUS_REG. *-------------------------------------------------------------- */ /* CODEC_CMD_REG: */ #define CODEC_CMD_VALID 0x00010000 /* Hw sets when cmd loaded, remains set */ /* till cmd is serially output to codec. */ #define CODEC_CMD_MASK 0xFF00FFFF /* Codec reg num | reg value. */ /* CODEC_STATUS_REG: */ #define CODEC_STATUS_VALID 0x00030000 /* Status (low 16-bits readable) AND "new".*/ /* "new" is set when low bits are written,*/ /* prior to first read. */ /* LM4549 AC97 compatible National Semiconductor codec registers and signatures. */ #define LM4549_RESET 0x00 #define LM4549_MASTER_VOLUME 0x02 #define LM4549_LINE_OUT_VOLUME 0x04 #define LM4549_MONO_VOLUME 0x06 #define LM4549_BEEP_VOLUME 0x0A #define LM4549_PHONE_VOLUME 0x0C #define LM4549_MIC_VOLUME 0x0E #define LM4549_LINE_IN_VOLUME 0x10 #define LM4549_CD_VOLUME 0x12 #define LM4549_VIDEO_VOLUME 0x14 #define LM4549_AUX_VOLUME 0x16 #define LM4549_PCM_OUT_VOLUME 0x18 #define LM4549_RECORD_SELECT 0x1A #define LM4549_RECORD_GAIN 0x1C #define LM4549_GENERAL_PURPOSE 0x20 #define LM4549_3D 0x22 #define LM4549_POWERDOWN 0x26 #define LM4549_EXTENDED_AUDIO 0x28 #define LM4549_EXTENDED_AUDIO_STATUS 0x2A #define LM4549_PCM_FRONT_DAC_RATE 0x2C /* Equiv to PCM's: AC97_REGEXT_FDACRATE 0x2c */ #define LM4549_PCM_ADC_RATE 0x32 /* Equiv to PCM's: AC97_REGEXT_LADCRATE 0x32 */ #define LM4549_VENDOR_ID1 0x7C #define LM4549_VENDOR_ID2 0x7E /* LM4549_RESET: */ #define LM_RESET_VAL 0x0D50 /* Read feature vector from reset reg. */ /* LM4549_VENDOR_ID1 and LM4549_VENDOR_ID2 values: */ #define NSC_ID1 0x4E53 #define NSC_ID2 0x4331